Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, increasing transistor density and thus decreasing transistor size has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, the optimization of source/drain regions has become complex. Conventional techniques that are employed to form the source regions and the drain regions can negatively impact the gate electrode structures. In particular, certain ion implantation techniques may cause thickening of a top portion of the gate electrode, resulting in a mushroom geometry in the gate electrode structures that could cause shorting upon formation of interconnects that electrically connect to the source region and the drain region of the gate electrode structures. An exemplary photograph of a gate electrode structure having a mushroom geometry is shown in FIG. 1. Also due to potential shorting upon formation of the interconnects, thicker spacers adjacent to the gate electrode structures may be required to ensure that the interconnects do not contact the gate electrode structures, especially when the mushroom geometry exists in the gate electrode structures.
Accordingly, it is desirable to provide methods of forming integrated circuits with minimized mushroom geometry in the gate electrode structures after formation of source regions and drain regions for the gate electrode structures. It is also desirable to minimize spacer thickness for spacers adjacent to the gate electrode structures while avoiding shorting, and to provide integrated circuits with the minimized spacer thickness. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.